Xilinx true dual port ram

. .

. This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below.

. Selectable Memory Algorithm The core concatenates block RAM primitives a ccording to one of the following algorithms.

.

This element can be configured and used as a 1-bit wide by 32K deep to. So, if I want to use both ports to do simultaneous Reads, on the exact same memory location, it should be okay, correct ><p><p><p> I know that you cannot do a simultaneous writeread on the same memory.